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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. ge ne ra l de sc ript ion the max2361 dual-band, triple-mode complete transmi t- ter for cellular phones represents an integrated an d archi- tecturally advanced solution for this application. the device takes a differential i/q baseband input and con- verts it up to if through a quadrature modulator an d if variable-gain amplifier (vga). the signal is then r outed to an external bandpass filter and upconverted to rf through an image-reject mixer and rf vga. the signa l is further amplified with an on-chip pa driver. an if synthe- sizer, an rf synthesizer, a local oscillator (lo) b uffer, and a 3-wire programmable bus complete the basic functi onal blocks of this ic. the max2363 supports single- band, sin- gle-mode (pcs) operation. the max2365 supports sin- gle-band cellular dual-mode operation. the max2361 enables architectural flexibility becau se of its two if voltage-controlled oscillators (vcos) , two if ports, two rf lo input ports, and three pa driver o utput ports. the devices allow the use of a single receiv e if frequency and split-band pcs filters for optimum ou t-of- band noise performance. the low-noise pa drivers allow up to three rf saw filters to be eliminated. select a mode of operation by loading data on the spi ? /qspi ? /microwire ? -compatible 3-wire serial bus. charge-pump current, if/rf gain balancing, standby, shutdown plus additional functions, are al so controlled with the serial interface. the max2361/max2363/max2365 come in a 48-pin tqfn-ep and qfn-ep package and are specified for the extended (-40c to +85c) temperature range. applic a t ions cdma, cdma2000?, tdma, w-cdma, gait mobile phones satellite phones wireless data links (wan/lan) wireless local area networks (lans) high-speed data modems fe a t ure s ? dual-band, triple-mode operation ? +9dbm linear output power ? 100db power-control range ? supply current drops as output power is reduced ? dual synthesizer for if and rf lo ? dual on-chip if vco ? qspi/spi/microwire-compatible 3-wire bus ? digitally controlled operational modes ? single sideband upconverter eliminates sawfilters ? directly drives power amplifier m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 ________________________________________________________________ maxim integrated products 1 ref n.c. n.c. tankh+ tankh- tankl+ tankl- iflo v cc shdn i- i+ rfl rfh0 lock v ccdrv idle v cc txgate ifinl+ ifinl- ifinh+ ifinh- bias 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 clk di cs ifouth- ifouth+ ifoutl- ifoutl+ gc v cc v cc q+ q- gnd rfh1 gnd gnd lol loh rfpll v ccrfcp rfcp v cc ifcp v ccifcp max2361 +45 -45 90 0 0 90 /2 ifpll rfpll /2 (t) qfn-ep 19-2013; rev 2; 7/04 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. cdma2000 is a trademark of telecommunications indus try association. pin configurations appear at end of data sheet.selector guide appears at end of data sheet. func t iona l dia gra m orde ring i nform a t ion * ep = exposed paddle. evaluation kit available com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs part temp range pin-package 48 qfn-ep* -40c to +85c max2361 egm max2363 egm -40c to +85c 48 qfn-ep* 48 qfn-ep* -40c to +85c max2365 egm 48 tqfn-ep* -40c to +85c max2365etm 48 tqfn-ep* -40c to +85c max2361etm max2363etm -40c to +85c 48 tqfn-ep* downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics ( max2361/max2363/max2365 , shdn = idle = txgate = high, v gc = 2.4v, r bias = 10k ? , i cc ctrl is in power-up state, no ac signals applied, v cc = +2.7v to +3.3v, v bat = +2.7v to +4.5v, t a = -40c to +85c, unless otherwise noted. typical v alues are at v cc = v bat = +2.8v, t a = +25c, and operating modes are defined in table 9 .) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. v cc to gnd ............................................. ..............-0.3v to +3.6v rfl, rfh0, rfh1, v ccifcp , v ccrfcp , v ccdrv to gnd ..................-0.3v to +5.5v di, clk, cs , gc, shdn , txgate , idle, lock to gnd ................................-0.3v to (v cc + 0.3v) ac input pins (ifinl_, ifinh_, q_, i_, tankl_, tank h_, ref, rfpll, lol, loh).............................. ............1.0v peak digital input current ( shdn , txgate , idle , clk, di, cs ) .................................................. ..............10ma continuous power dissipation (t a = +70c) 48-pin qfn-ep (derate 27mw/c above +70c) ..............2.1w operating temperature range ........................ ...-40c to +85c junction temperature ............................... .......................+150c storage temperature range .......................... ...-65c to +150c lead temperature (soldering, 10s) .................. ...............+300c parameter conditions min typ max units v cc 2.7 3.3 operating supply voltage v bat 2.7 4.5 v v gc = 0.6v 50 82 v gc = 1.95v 55 90 p rfh0 = +5dbm 114 mpl = 0 p rfh1 = +5dbm 121 p rfh0 = +8dbm 137 pcs mode mpl = 1 p rfh1 = +8dbm 146 v gc = 0.6v 48 78 v gc = 1.95v 53 86 mpl = 0, p rfl = +5dbm 102 cellular mode mpl = 1, p rfl = +8dbm 126 v gc = 1.95v 75 85 fm mode mpl = 1, p rfl = +11dbm 87 addition for iflo buffer 3.4 7.7 idle = low, pss = 0 6 10 idle = low, pss = 1 7.2 12.2 operating supply current txgate = low, rfpll off 11 17 ma leakage current shdn = low, rfh_, rfl, v ccdrv 0.5 20 a logic high 0.7v cc v logic low 0.3v cc v logic input current -5 +5 a gc input current 61 1 a gc input resistance during shutdown shdn = low 215 340 k ? lock indicator high 100k ? pullup load v cc - 0.4 v lock indicator low 100k ? pullup load 1.0 v downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs _______________________________________________________________________________________ 3 electrical characteristics ( max2361/max2363/max2365 ev kit , 50 ? system, operating modes as defined in table 9, temp _comp = 10, input voltage at i and q = 600mv p-p differential, 300khz quadrature cw tones, rf and if synthesizers locked, v ref = 200mv p-p at 19.68mhz, v cc = v bat = shdn = idle = cs = txgate = 2.8v, loh, lol input power = -10dbm, f lol = 966.38mhz, f loh = 1750mhz, f rfh0 = f rfh1 = 1880.38mhz, f rfl = 836mhz, t a = +25c, unless otherwise noted.) parameter conditions min typ max units modulator, quadrature modes (cdma, pcs, fm_iq) if_sel = 0 120C235 if frequency range if_sel = 1 120C380 mhz i/q common-mode input voltage v cc = +2.7v to +3.3v (notes 1, 2, 3) 1.35 v cc / 2 v cc - 1.25 v i_/q_ input current common-mode voltage = 1.4v 6 a if gain-control range v gc = 0.6v to 2.4v, ifg = 100 85 db if output power at ifoutl and ifouth ifg = 100, acpr = -60dbc (note 4) -7 dbm gain variation over temperature relative to +25c, t a = -40c to +85c (note 1) -1 +1 db carrier suppression v gc = 2.4v, ifg = 100, f ifoutl = 130.38mhz (note 1) 35 43 db sideband suppression v gc = 2.4v, ifg = 100, f ifoutl = 130.38mhz (note 1) 35 45 db if output noise v gc = 2.4v, noise measured at 20mhz offset -143 dbm/ hz modulator, fm mode v gc = 2.4v, ifg = 100, i/q modulation -9 output power at ifoutl v gc = 2.4v, ifg = 100, direct vco modulation -4 dbm upconverter and predriver if_sel = 0 120C235 if frequency range if_sel = 1 180C380 mhz rfl frequency range rfl port 800C1000 mhz rfh_ frequency range rfh0 and rfh1 ports 1700C2000 mhz lol frequency range 800C1150 mhz loh frequency range 800C2360 mhz lo input power lol, loh -10 -7 dbm pss = 0 1300 rfpll frequency range pss = 1 2360 mhz rfl 19.2 rfh0 18.9 mpl = 0, t a = -40 c to +85 c rfh1 17.6 rfl 22.4 rfh0 22.8 conversion gain mpl = 1, t a = -40 c to +85 c rfh1 21.4 db rf gain-control range v gc = 0.6v to 2.4v 40 db image signal at maximum output power -35 dbc downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 4 _______________________________________________________________________________________ electrical characteristics (continued) ( max2361/max2363/max2365 ev kit , 50 ? system, operating modes as defined in table 9, temp _comp = 10, input voltage at i and q = 600mv p-p differential, 300khz quadrature cw tones, rf and if synthesizers locked, v ref = 200mv p-p at 19.68mhz, v cc = v bat = shdn = idle = cs = txgate = 2.8v, loh, lol input power = -10dbm, f lol = 966.38mhz, f loh = 1750mhz, f rfh0 = f rfh1 = 1880.38mhz, f rfl = 836mhz, t a = +25c, unless otherwise noted.) parameter conditions min typ max units cascaded modulator, upconverter, and predriver rfl output power mpl = 1, t a = -40 c to +85 c, meets acpr specifications (note 1) 6.8 9 dbm rfh0 output power mpl = 1, t a = -40 c to +85 c, meets acpr specifications (note 1) 7.7 10.7 dbm rfh1 output power mpl = 1, t a = -40 c to +85 c, meets acpr specifications (note 1) 6.6 9.7 dbm rfl adjacent channel power ratio f offset = 885khz in 30khz bandwidth -52 dbc rfl alternate channel power ratio f offset = 1.98m h z i n 30kh z b and w i d th -65 dbc rfh_ adjacent channel power ratio f offset = 1.25m h z i n 30kh z b and w i d th -52 dbc rfh_ alternate channel power ratio f offset = 1.98m h z i n 30kh z b and w i d th -68 dbc mpl =1, p rfl = +8dbm -131 -128 mpl =0, p rfl = +5dbm noise measured at +45mhz offset -134 -131 mpl =1, p rfh_ = +8dbm -131 -128 rx band noise power (note 1) mpl =0, p rfh_ = +5dbm noise measured at +80mhz offset -133 -130 dbm/ hz output power variation over temperature relative to +25c, t a = -40c to +85c 1 db if_pll reference frequency 5 30 mhz reference frequency signal level 0.1 0.6 v p-p if main divide ratio 256 16383 if reference divide ratio 2 2047 vco_sel =0 240C470 vco operating range vco_sel =1 240C760 mhz icp = 00 114 139 178 icp = 01 158 192 246 icp = 10 228 278 356 charge-pump source/sink current icp = 11 319 390 499 a downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs _______________________________________________________________________________________ 5 note 1: guaranteed by design and characterization to 3 sigm a (includes board and component variations). note 2: acpr is met over the specified v cm range. note 3: v cm must be supplied by the i/q baseband source with 8 a capability. note 4: iq_level = 0, v q _ = v i _ = 87mv rms differential, is98 reverse channel modulation at 41 5mvp-p differential with 0.1% 4.5db peak-to-average ratio. note 5: when enabled with rcp_turbo1 and rcp_turbo2 (see ta bles 2 and 3), the total charge-pump current is spe cified. for all values of rcp, the total turbolock current is 1.63 times the corresponding nonturbo current value. electrical characteristics (continued) ( max2361/max2363/max2365 ev kit , 50 ? system, operating modes as defined in table 9, temp _comp = 10, input voltage at i and q = 600mv p-p differential, 300khz quadrature cw tones, rf and if synthesizers locked, v ref = 200mv p-p at 19.68mhz, v cc = v bat = shdn = idle = cs = txgate = 2.8v, loh, lol input power = -10dbm, f lol = 966.38mhz, f loh = 1750mhz, f rfh0 = f rfh1 = 1880.38mhz, f rfl = 836mhz, t a = +25c, unless otherwise noted.) parameter conditions min typ max units turbolock boost current icp_max = 1 632 774 987 a charge-pump source/sink matching all values of icp, over specified compliance range 6 % if charge-pump compliance 0.5 v ccifcp - 0.5 v charge-pump high-z leakage over specified compliance range 20 pa rf_pll reference frequency 5 30 mhz rf main divide ratio 4096 262143 rf reference divide ratio 2 8191 rcp = 00 266 325 416 rcp = 01 533 650 832 rcp = 10 605 738 945 charge-pump source/sink current rcp = 11 872 1063 1361 a turbolock boost current (note 5) 1388 1694 2168 a charge-pump source/sink matching all values of rcp, over specified compliance range 6 % rf charge pump compliance 0.5 v ccrfcp - 0.5 v phase detector noise floor rcp = 11, rcp_turbo1 = rcp_turbo2 = 0, 30khz comparison frequency -162 dbc/hz charge-pump high-z leakage over specified compliance range 20 pa rfpll input sensitivity 160 mv p-p downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 6 _______________________________________________________________________________________ -80 -50 -60 -70 -40 -30 -20 -10 0 10 20 2.0 2.1 2.2 2.3 2.4 output power, acpr vs. v gc (rfl) max2361 toc01 v gc (v) p out (dbm), acpr/altr (dbc) f rfl = 836mhz mpl = 1 p out alternate adjacent -80 -50 -60 -70 -40 -30 -20 -10 0 10 20 2.0 2.1 2.2 2.3 2.4 output power, acpr vs. v gc (rfh1) max2361 toc02 v gc (v) p out (dbm), acpr/altr (dbc) f rfh1 = 1880mhz mpl = 1 p out alternate adjacent -80 -50 -60 -70 -40 -30 -20 -10 0 10 20 2.0 2.1 2.2 2.3 2.4 output power, acpr vs. v gc (rfh0) max2361 toc03 v gc (v) p out (dbm), acpr/altr (dbc) f rfho = 1880mhz mpl = 1 p out alternate adjacent 40 80 60 120 100 140 160 2.0 2.2 2.1 2.3 2.4 supply current vs. v gc max2361 toc04 v gc (v) supply current (ma) mpl = 1 r fh0 , r fh1 rfl -20 -30 -40 -50 -60 100 250 150 200 300 350 400 if im age rejection max2361 toc05 if frequency (mhz) rejection (dbc) image rejection lo rejection measured at ifouth -60 -50 -30 -40 -20 -10 130 170 190 150 210 230 250 270 290 rf im age rejection from ifinl max2361 toc06 if frequency (mhz) rejection (dbc) measured at rfl, f lo = 836mhz + f if corrected for rfl frequency response combined performance of image rejection and rfl frequency response -10 -20 -30 -40 -50 180 300 220 260 340 380 rf im age rejection from ifinh max2361 toc07 if frequency (mhz) rejection (dbc) measured at rfh0, f lo = 1880mhz + f if corrected for rfh0 frequency response combined performance of image rejection and rfh0 frequency response typic a l ope ra t ing cha ra c t e rist ic s (max2361 ev kit, v cc = v bat = +2.8v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs _______________________________________________________________________________________ 7 -50 -35 -40 -45 -30 -25 -20 -15 -10 -5 0 1.8 2.0 1.9 2.1 2.2 2.3 2.4 if output power vs. v gc max2361 toc10 v gc (v) if output power (dbm) t a = -40 c, +25 c, +85 c ifg = 100, include if balun loss -50 -35 -40 -45 -25 -30 -5 -10 -15 -20 0 01234567 if power vs. ifg setting max2361 toc11 ifg control code (dec.) if power (dbm) v gc = +2.4v v gc = +2.3v v gc = +2.0v include if balun loss -80 -70 -75 -60 -65 -50 -55 -45 20 28 24 32 36 40 cascaded acpr and altr vs. i ccpa (rfl) max2361 toc12 i ccpa (ma) acpr, altr (dbc) adjacent alternate measured at rfl, ifg = 101, mpl = 1, f rfl = 836mhz, p rfl = +8dbm -80 -75 -70 -65 -60 -55 -50 -45 -40 22 26 30 34 38 42 cascaded acpr and altr vs. i ccpa (rfh0) max2361 toc13 i ccpa (ma) acpr, altr (dbc) adjacent alternate measured at rfho, ifg = 101, mpl = 1, f rfh0 = 1880mhz, p rfh0 = +8dbm -3.0 -2.0 -2.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 if gain flatness vs. frequency max2361 toc08 if frequency (mhz) normalized if gain flatness (db) 100 200 250 150 300 350 400 measured at rf outputs, f rfl = 836mhz, f rfh1 = 1880mhz, p ifin_ = -10dbm differential, v gc = +2.4v, include if balun loss ifinh ifinl -50 -35 -40 -45 -30 -25 -20 -15 -10 -5 0 1.8 2.0 1.9 2.1 2.2 2.3 2.4 if output power vs. v gc max2361 toc09 v gc (v) if output power (dbm) v cc = +2.7v, +2.85v, +3.3v ifg = 100, include if balun loss typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (max2361 ev kit, v cc = v bat = +2.8v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 8 _______________________________________________________________________________________ frequency offset (hz) phase noise vs. frequency offset tankl oscillator -50 -60 -80 -70 max2361 toc14 -90 -100 -110 -120 -130 -140 -150 phase noise (dbc/hz) 1k 10k 100k 1m 10m vco oscillates at 260mhz, phase noise measured at iflo with buf_div = 1 frequency offset (hz) phase noise vs. frequency offset tankh oscillator -50 -60 -80 -70 max2361 toc15 -90 -100 -110 -120 -130 -140 -150 phase noise (dbc/hz) 1k 10k 100k 1m 10m vco oscillates at 340mhz, phase noise measured at iflo with buf_div = 1 time ( s) 200 0 400 600 800 1000 if pll lock tim e icp = 11, icp_max = 0 f comp = 240khz, f if = 263.64mhz loop filter: 20k ? in series with 2.2nf, 220pf parallel loop bw = 10khz 10khz -10khz 2khz/div max2361 toc16 lol port s 11 max2361 toc17 1: 1ghz: 74.9 ? - j34.4 ? 2: 800mhz: 81 ? - j37.4 ? start: 700mhz stop: 2.5ghz 1 2 loh port s 11 max2361 toc18 1: 2.36ghz: 37.2 ? - j16.8 ? 2: 800mhz: 80 ? - j38.9 ? 1 2 start: 700mhz stop: 2.5ghz rfpll port s 11 max2361 toc19 1: 2.36ghz: 38.3 ? - j20.2 ? 2: 800mhz: 70.4 ? - j61.6 ? 1 2 start: 700mhz stop: 2.5ghz typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (max2361 ev kit, v cc = v bat = +2.8v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs _______________________________________________________________________________________ 9 pin de sc ript ion 13, 14, 15 13, 14, 15 13, 14, 15 clk, di, cs input pins from the 3-wire serial bus (spi/qspi/mic rowire compatible) bias resistor pin. bias is internally biased to app roximately 600mv. an exter- nal resistor between this pin to gnd sets the bias current for the upconverters and pa driver stages. the nominal resistor value is 10k ? . this value can be altered to optimize the linearity of the driver sta ge. bias 12 12 12 10, 11 10, 11 ifinh+, ifinh- differential inputs to the rf upconverter. these pi ns are internally biased. the input impedance for these ports is nominally 40 0 ? differential. the if fil- ter should be ac-coupled to these ports. keep the d ifferential lines as short as possible to minimize stray pickup and shunt capa citance. differential inputs to the rf upconverter. these pi ns are internally biased. the input impedance for these ports is nominally 40 0 ? differential. the if fil- ter should be ac-coupled to these ports. keep the d ifferential lines as short as possible to minimize stray pickup and shunt capa citance. ifinl+, ifinl- 8, 9 8, 9 7 7 7 txgate digital input, drive to logic high for normal opera tion. a logic low on txgate shuts down everything except the rf pll, if pll, if vco, and seri- al bus and registers. this mode is used for gated t ransmission. supply pin for the upconverter stage. v cc must be bypassed to system ground as close to the pin as possible. the ground vias for the bypass capacitor should not be shared by any other branch. v cc 6 6 6 5 5 5 idle digital input, drive to logic high for normal opera tion. a logic low on idle shuts down everything except the rf pll and associa ted registers. a small r-c lowpass can be used to filter digital noise. supply pin for the driver stage. may be connected d irectly to the battery. bypass to pc board ground as close to the pin as po ssible. the ground vias for the bypass capacitor should not be shared by an y other branch. v ccdrv 4 4 4 3 3 3 lock open-collector output indicating lock status of the if and/or the rf plls. requires a pullup resistor. control using configura tion register bits ld_mode. transmitter rf output for pcs band (1700mhz to 2000 mhz). this open- collector output requires a pullup inductor to the supply voltage. the pullup inductor may be part of the output matching network and may be connected directly to the battery. for split band pcs applica tion, use rfh0 for the 1880mhzC1910mhz range. rfh0 2 2 transmitter rf output for cellular band (800mhz to 1000mhz)for both fm and digital modes. this open-collector output requi res a pullup inductor to the supply voltage, which may be part of the output matching network and can be connected directly to the battery. rfl 1 1 max2361 max2365 function name pin max2363 downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 10 ______________________________________________________________________________________ pin de sc ript ion (c ont inue d) pin max2361 max2363 max2365 name function 16, 17 16, 17 ifouth-, ifouth+ differential if outputs. these ports are active whe n the register bit if_sel is 1. they do not support fm mode. these pins must be inductively pulled up to v cc . a differential if bandpass filter is connected be tween this port and ifinh+ or ifinh-. the pullup inductors can be part of the filter structure. the differential output impedance of this port is nomin ally 600 ? . the transmission lines from these pins should be short to minimize t he pickup of spurious sig- nals and noise. 18, 19 18, 19 ifoutl-, ifoutl+ differential if outputs. these ports are active whe n the register bit if_sel is 0. these pins must be inductively pulled up to v cc . a differential if band- pass filter is connected between this port and ifin l+ and ifinl-. the pullup inductors can be part of the filter structure. the differential output impedance of this port is nominally 600 ? . the transmission lines from these pins should be short to minimize the pickup of spurious signals and noise. 20 20 20 gc rf and if gain control analog input. apply 0.6v to 2.4v to control the gain of the rf and if stages. an rc filter on this pin shou ld be used to reduce dac noise or pdm clock spurs from this line. 21 21 21 v cc supply pin for the if vga. bypass with a capacitor as close to the pin as possible. the bypass capacitor must not share its g round vias with any other branches. 22 22 22 v cc supply for the i/q modulator. bypass with a capacit or as close to the pin as possible. the bypass capacitor must not share its g round vias with any other branches. 23, 24 23, 24 23, 24 q+, q- differential q-channel baseband inputs to the modul ator. these pins go directly to the bases of a differential pair and re quire an external common- mode bias voltage. 25, 26 25, 26 25, 26 i+, i- differential i-channel baseband inputs to the modul ator. these pins go directly to the bases of a differential pair and re quire an external common- mode bias voltage. 27 27 27 shdn shutdown input, drive to logic high for normal oper ation. a logic low on shdn shuts down the entire ic except the serial interfac e and retains the information in all registers. an r-c lowpass can be used to filter digital noise. 28 28 28 v cc supply pin to the vco section. bypass as close to t he pin as possible. the bypass capacitor should not share its vias with any other branches. 29 29 29 iflo buffered lo output. control the output buffer using register bit buf_en and the divide ratio using the register bit buf_div. 30, 31 30, 31 tankl-, tankl+ differential tank pins for the low-frequency if vco . these pins are internally biased. vco_sel = 0 selects this if vco. downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 11 pin de sc ript ion (c ont inue d) 34, 35 1, 8, 9, 18, 19, 30, 31, 34, 35, 44 no connection. make no connection to these pins. 2, 10, 11, 16, 17, 32C35 43, 47 n.c. max2361 max2363 function 32, 33 32, 33 differential tank pins for the high-frequency if vc o. these pins are internally biased. vco_sel = 1 selects this if vco. 39 39 supply pin for digital circuitry. bypass as close t o the pin as possible. the bypass capacitor must not share its vias with any o ther branch. 38 38 high-impedance output of the if charge pump. connec t to the tune input of the if vcos through the if pll loop filter. keep th e line from ifcp to the tune input as short as possible to prevent spurious pick -up, and connect the loop filter as close to the tune input as possible. 37 37 supply for the if charge pump. this supply can diff er from the system v cc . bypass as close to the pin as possible. the bypass capacitor must not share its vias with any other branches. 36 36 reference frequency input. ref is internally biased and must be ac-cou- pled to the reference source. this is a high-impeda nce port (25k ? ii 3pf). 44 low-band rf lo input port. ac-couple to this port. 43 43 high-band rf lo input port. ac-couple to this port. 42 42 rf pll input. ac-couple this port to the rf vco. rf pll is internally biased. 41 41 supply for the rf charge pump. this supply can diff er from the system v cc . bypass as close to the pin as possible. the bypass capacitor must not share its vias with any other branches. 40 40 high-impedance output of the rf charge pump. connec t to the tune input of the rf vcos through the rf pll loop filter. keep the line from this pin to the tune input as short as possible to prevent spur ious pickup, and connect the loop filter as close to the tune input as possi ble. pin max2365 39 38 37 36 44 42 41 40 name tankh-, tankh+ v cc ifcp v ccifcp ref lol loh rfpll v ccrfcp rfcp 45, 46, 48 45, 46, 48 isolation gnd. no internal connection. connect to p c board ground plane for better isolation. 45, 46, 48 gnd 47 47 transmitter rf output for pcs band (1700mhz to 2000 mhz). this open-col- lector output requires a pullup inductor to the sup ply voltage. the pullup inductor may be part of the output matching network and can be connected directly to the battery. for split band pcs applica tion, use rfh1 for the 1850mhzC1880mhz range. rfh1 ep ep dc and ac gnd return for the ic. connect to pc boar d ground plane using multiple vias. ep gnd downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 12 ______________________________________________________________________________________ de t a ile d de sc ript ion the max2361 complete quadrature transmitter accepts differential i/q baseband inputs with external comm on- mode bias. a modulator upconverts this to if freque ncy in the 120mhz to 380mhz range. a gain-control volta ge pin (gc) controls the gain of both the if and rf vg as simultaneously to achieve the best current consumpt ion and linearity performance. the if signal is brought off- chip for filtering, then fed to a single sideband u pcon- verter followed by the rf vga and pa driver. the rf upconverter requires an external vco for operation. the if pll, rf pll, and operating mode can be pro- grammed by an spi/qspi/microwire-compatible 3- wire interface. the following sections describe each block in the max2361 functional diagram. i /q m odula t or differential in-phase (i) and quadrature-phase (q) input pins are designed to be dc-coupled and biased with the baseband output from a digital-to-analog converter (dac). i and q inputs need a dc bias of v cc /2 and a current-drive capability of 8a. the i and q inputs capacitance is typically 0.3pf differential. common - mode voltage works within a 1.35v to (v cc - 1.25v) range. the if vco output is fed into a divide-by- two/quadrature generator block to derive quadrature lo components to drive the iq modulator. the output of the modulator is fed into the vga. i f v cos there are two vcos to support high if and low if fr e- quencies. the vcos oscillate at twice the desired i f fre- quency. oscillation frequency is determined by exte rnal tank components (see applications information ). typical phase-noise performance for the tank is as shown in the typical operating characteristics . the high-band and low-band vcos can be selected independently of the if port being used. i flo out put buffe r iflo provides a buffered lo output when buf_en is 1 . the iflo output frequency is equal to the vco fre- quency when buf_div is 0, and half the vco frequen- cy when buf_div is 1. the output power is -12dbm. this output is intended for applications where the receive if is the same frequency as the transmit if . i f/rf pll the if/rf pll uses a charge-pump output to drive a loop filter. the loop filter typically is passive s econd- order lead lag filter. outside the filters bandwid th, phase noise is determined by the tank components. the two components that contribute most significant ly to phase noise are the inductor and varactor. use h igh- q inductors and varactors to maximize equivalent pa r- allel resistance. the if_turbo_charge, rcp_turbo1, and rcp_turbo2 bits can be set to enable turbo mode. turbo mode provides maximum charge-pump current during frequency acquisition. turbo mode is disabled after frequency acquisition is achieved. when turbo mode is disabled, charge-pump current returns to the programmed levels as set by icp and rcp bits in the config register (table 3). the pss bit selects the rfpll prescaler speed inde- pendent of the mode bits. this enables pcs band vco locking when transmitting in the cellular band. for vco frequency above 1300mhz, set pss to 1. i f v ga the if vga allows varying an if output level that i s con- trolled by gc voltage. the voltage range on gc of 0 .6v to 2.4v provides a gain-control range of 85db. ther e are two differential if output ports from the vga. ifoutl+/ifoutl- are optimized for low if operation (120mhz to 235mhz); ifouth+/ifouth- support high if operation (120mhz to 380mhz). ifoutl supports fm mode by providing higher if output level when mode is set to 00. single side ba nd m ix e r the rf transmit mixer uses a single sideband archit ec- ture to eliminate an off-chip rf filter. the single sideband mixer has if input stages that correspond to if out put ports of the vga. the mixer is followed by the rf v ga. the rf vga is controlled by the same gc pin as the if vga to provide optimum current consumption and line ar- ity performance. the total power-control range is >100db. pa drive r the max2361 includes three power-amplifier (pa) dri - vers. each is optimized for the desired operating f re- quency. rfl is optimized for cellular-band operatio n. rfh0 and rfh1 are optimized for split-band pcs oper a- tion. use rfh0 in single high-band output such as tdma or w-cdma. the pa drivers have open-collector outputs and require pullup inductors. the pullup in duc- tors can act as the shunt element in a shunt series match. downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 13 progra m m a ble re gist e rs the max2361/max2363/max2365 include eight pro- grammable registers consisting of four divide regis ters, a configuration register, an operational control re gister, a current control register, and a test register. ea ch reg- ister consists of 24 bits. the 4 least significant bits (lsbs) are the registers address. the 20 most sign ifi- cant bits (msbs) are used for register data. all re gisters contain some don't care bits. these can be either a 0 or a 1 and will not affect operation (figure 1). data is shifted in msb first, followed by the 4-bit addr ess. when cs is low, the clock is active and data is shifted with the rising edge of the clock. when cs transitions to high, the shift register is latched into the regist er select- ed by the contents of the address bits. power-up defaults for the eight registers are shown in table 1. the dividers and control registers are programmed from the spi/qspi/microwire-compatible serial port. the rfm register sets the main frequency divide rat io for the rf pll. the rfr register sets the reference fre- quency divide ratio. the rf vco frequency can be determined by the following: rf vco frequency = f ref ? (rfm / rfr) ifm and ifr registers are similar: if vco frequency = f ref ? (ifm / ifr) where f ref is the external reference frequency. the operational control register (opctrl) controls the state of the max2361/max2363/max2365. see table 2 for the function of each bit. the configuration register (config) sets the config ura- tion for the rf/if pll and the baseband i/q input l ev- els. see table 3 for a description of each bit. the current control register modifies the bias curr ent to accommodate different operation modes. in the high- power mode, mpl = 1 sets the bias current and con- version gain to deliver a minimum of +8dbm output power from the pa drivers. in the low-power mode, mpl = 0 sets the bias current and conversion gain t o deliver a minimum of +5dbm output power from the pa drivers. i_mult sets the current multiplication fac tor for the pa driver stages according to table 5. throt- tle_back sets the rate of bias current changes when the output power changes according to table 6. for example, when throttle_back = 011 (default), the pa driver bias current reduces by 1dbma for every 1db reduction in output power. throttle_back = 000 setting gives a more aggressive current reducti on (1.3dbma/db power) at the expense of linearity. throttle_back setting does not affect the bias cur- rent at maximum power level. the test register has to be 100hex for normal opera tion. the best way to ensure this is to program the test regis- er to 100hex. power management bias control is distributed among several functiona l sections and can be controlled to accommodate many different power-down modes as shown in table 8. the serial interface remains active during shutdown . setting shdn_bit = 0 or shdn = gnd powers down the device. in either case, pll programming and reg is- ter information is retained. signal flow control table 9 shows an example of key registers for tripl e- mode operation, assuming half-band pcs and if fre- quencies of 228.6mhz/263.6mhz. applic a t ions i nform a t ion the max2361 is designed for use in dual-band, tripl e- mode systems. it is recommended for triple-mode han d- sets (figure 2). the max2363 is designed for use in cdma pcs handset or w-cdma systems (figure 3). the max2365 is designed for use in dual-mode cellul ar systems (figure 4). table 1. register power-up default states test 0111 b 100 hex test-mode control config opctrl ifr 0101 b 0100 b 0011 b 0492 dec 090f hex d03f hex ifm rfr rfm register 0010 b 0001 b 0000 b address default 32214 dec 656 dec 6519 dec configuration and setup control operational control settings if r divider count if m divider count rf r divider count rf m divider count function i cc ctrl 0110 b 0038 hex current multiplication factor, pll band downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 14 ______________________________________________________________________________________ ca sc a de d pe rform a nc e tables 11 and 12 show the typical cascaded perfor- mance for tdma and w-cdma systems. 3 -wire i nt e rfa c e figure 5 shows the 3-wire interface timing diagram. the 3-wire bus is spi/qspi/microwire compatible. ele c t rom a gne t ic com plia nc e conside ra t ions two major concepts should be employed to produce a low-spur and emc-compliant transmitter: minimize ci r- cular current-loop area to reduce h-field radiation . to minimize circular current-loop area, bypass as clos e to the part as possible and use the distributed capaci - tance of a ground plane. to minimize voltage drops, make v cc traces short and wide, and make rf traces short. program only the necessary bits in any register to mini- mize clock cycles. rc filtering can also be used to slow the clock edges on the 3-wire interface, reducing h igh- frequency spectral content. rc filtering also provi des for transient protection against iec802 testing by shunt- ing high frequencies to ground, while the series re sis- tance attenuates the transients for error-free oper ation. the same applies to the logic input pins ( shdn , txgate , idle ). figure 1. register configuration msb 24 bit register lsb data 20 bits address 4 bits b18 b16 b19 b17 b14 b12 b15 b13 b10 b8 b11 b9 b6 b4 b7 b5 b2 b0 b3 b1 a2 a0 a3 a1 rfm divide ratio (18) address x b16 x b17 b14 b12 b15 b13 b10 b8 b11 b9 b6 b4 b7 b5 b2 b0 b3 b1 0 0 0 0 rfm divide register rfr divide ratio (13) address x x x x x b12 x x b10 b8 b11 b9 b6 b4 b7 b5 b2 b0 b3 b1 0 1 0 0 rfr divide register ifm divide ratio (14) address x x x x x b12 x b13 b10 b8 b11 b9 b6 b4 b7 b5 b2 b0 b3 b1 0 0 0 1 ifm divide register ifr divide ratio (11) address x x x x x x x x b10 b8 x b9 b6 b4 b7 b5 b2 b0 b3 b1 0 1 0 1 ifr divide register operation control bits (16) address x x x x b14 b12 b15 b13 b10 b8 b11 b9 b6 b4 b7 b5 b2 b0 b3 b1 1 0 0 0 control register configuration bits (16) address x x x x b14 b12 b15 b13 b10 b8 b11 b9 b6 b4 b7 b5 b2 b0 b3 b1 1 1 0 0 configuration register test register current control register x = dont care 1 0 1 1 b1 b3 b0 b2 b5 b7 b4 b6 x x b8 x x x x x x x x x address 1 0 0 1 b1 b3 b0 b2 b5 b7 b4 b6 b9 b11 b8 b10 b13 b12 b15 x x x x address current control bits (16) b14 test bits (9) downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 15 buf_en 0 bit name power-up state function lo_sel 0 0 selects lol input port; 1 selects loh port. 4 rcp_turbo1 0 works in conjunction with rcp_turbo2 (config regist er) to set the turbo- charge pump mode. (see table 7) icp_max 0 1 keeps if turbo-mode current active even when freq uency acquisition is achieved. this mode is used when high operating if charge-pump current is needed. mode 01 sets operating mode according to the following: 00 = fm mode 01 = cellular digital mode, rfl is selected 10 = lower half-band pcs mode, rfh1 is selected 11 = upper half-band pcs, rfh0 is selected side_band 0 when this bit is 1, the upper sideband is selected (lo below rf). when this bit is 0, the lower sideband is selected (lo above rf). ifg 100 3-bit if gain control. alters if gain by approximat ely 2db per lsb (0 to 14db). provides a means for adjusting balance between rf a nd if gain for optimized linearity. vco_sel 0 1 selects high-band if vco; 0 selects low-band if v co. if_sel 0 1 selects ifinh and ifouth; 0 selects ifinl and ifo utl. for fm mode (mode = 00), set if_sel to 0. 0 turns iflo buffer off; 1 turns iflo buffer on. 15 14 13 12, 11 5 8, 7, 6 9 10 mod_type 1 3 0 selects direct vco modulation. (if vco is externa lly modulated and the i/q modulator is bypassed); 1 selects quadrature modula tion. stby 1 2 0 shuts down everything except registers and serial interface. txstby 1 1 0 shuts down modulator and upconverter, leaving pll s locked and registers active. this is the programmable equivalent to the txgate pin. shdn_bit 1 0 0 shuts down everything except serial interface, an d also retains all register settings. table 2. operation control register (opctrl) bit location (0 = lsb) downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 16 ______________________________________________________________________________________ table 3. configuration register (config) bit location (0 = lsb) power-up state determines output mode for lock detector pin as fol lows: 00 = test mode, ld_mode cannot be 00 for normal ope ration 01 = if pll lock detector 10 = rf pll lock detector 11 = logical and of if pll and rf pll lock detector s 1, 0 11 ld_mode works in conjunction with rcp_turbo1 (opctrl regist er) to set the turbo- charge current mode. (see table 7). 2 1 rcp_turbo2 1 activates turbocharge feature, providing an addit ional if charge-pump cur- rent during frequency acquisition. 3 1 if_turbo_ charge rf phase-detector polarity; 1 selects positive pola rity (increasing tuning voltage on the vco produces increasing frequency); 0 select s negative polarity (increasing voltage on the vco produces decreasing frequency). 4 1 rf_pd_pol if phase-detector polarity; 1 selects positive pola rity (increasing tuning voltage on the vco produces increasing frequency); 0 select s negative polarity (increasing tuning voltage on the vco produces decr easing frequency). 5 1 if_pd_pol 7, 6 12 11 10 9, 8 13 14 15 a 2-bit register sets the rf charge-pump current as follows: 00 = 325a 01 = 650a 10 = 738a 11 = 1063a 00 rcp 1 selects 200mv rms input mode; 0 selects 100mv rms input mode. 1 iq_level 1 selects 2 on iflo port; 0 bypasses the divider. 0 buf_div 1 bypasses if vco and enables a buffered input for external vco use. 0 vco_bypass a 2-bit register sets the if charge-pump current as follows: 00 = 139a 01 = 192a 10 = 278a 11 = 390a 00 icp 0 for normal operation, 1 turns off the bias curren t to rfh0 output driver. 0 zero_bias 0 shuts down the rf pll. this mode is used with an external rf pll. 1 rf_pll_ shdn 0 shuts down the if pll. this mode is used with an external if pll. 1 if_pll_shdn function bit name downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 17 table 4. current control register (i cc ctrl) table 5. current scale factors setby i_mult bits bit name power- up state bit location (0 = lsb) function reserved 00 15, 14 must be set to 00 for normal opera tion. pss 0 13 prescaler speed select. 0 selects the lower frequen cy band rfpll prescaler. 1 selects the higher frequency band pres caler. reserved 0 12 must be set to 0 for normal operation. mpl 0 11 sets the maximum output power level. 0 selects +6.5 dbm, 1 selects +10dbm output power modes. temp_comp 00 10, 9 sets current scale factor to compensate temperature variations. set to 10 for best linearity over temperature. reserved 0 8 must be set to 0 for normal operation. mod_bypass 0 7 1 routes differential signal at pins 30 and 31 dire ctly to the if vga and bypasses the if modulator. this mode is used with e xternal modulator. throttle_back 011 6, 5, 4 throttle back rate (table 6) i_mult 1000 3, 2, 1, 0 sets current scale factor for pa drivers (table 5) bit name bits current scale 0000 0.50 0001 0.56 0010 0.62 0011 0.69 0100 0.75 0101 0.81 0110 0.88 0111 0.94 1000 (default) 1.00 1001 1.13 1010 1.25 1011 1.38 1100 1.50 1101 1.63 1110 1.75 i_mult 1111 1.88 bit name bits rate unit 000 1.3 001 1.2 010 1.1 011 (default) 1.0 100 0.9 101 0.8 110 0.7 th rottle _bac k 111 0.6 dbma/db table 6. throttle-back rate setby throttle_back bits downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 18 ______________________________________________________________________________________ table 8. power-down modes x = off table 7. rf turbo charge-pump current setting rcp_turbo1 rcp_turbo2 0 0 no turbo current. charge-pump current is set by r cp bits. 01 turbo current turns on every time rfpll is reprogra mmed. turbo current is automatically turned off after rfpll is locked. 1 0 turbo current is always on. 1 1 turbo current is turned on every time rfpll is ou t of lock. x if pll shdn for external if pll use x x x x x x x txstby bit rf pll shdn txgate pin x for punctured tx mode for external rf pll use tx is off, but if and rf los stay locked idle pin x shdn pin power-down mode x ultra-low shutdown current rx only mode x x x x if_pll comments if vco rf pll modulator upconverter downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 19 1 0 1 h 0 0 0 pcs lower half-band, rfh1 selected gated transmission, cellular digital pcs upper half-band, rfh0 selected cellular txgate 1 10 01 pcs high 11 pcs low listen for pages rx on, tx off direct vco modulation, rfl selected rfl selected x 0x 00 cellular digital fm cellular idle 01 gated transmission, pcs 1x pcs txgate 1 0 1 ultra-low current 0 0 0 1 1 0 1 sleep 0 0 0 1 1 1 1 xx x 0 1 1 1 1 1 x 1 1 1 1 1 x 1 x x 1 1 x 1 1 1 1 1 1 1 1 1 1 x x 1 1 1 1 1 1 x 1 1 1 1 h h h x l h h h h l h x h h h l 1 listen for pages rx on, tx off 1x pcs idle 1 1 1 1 x 1 x 1 l h lo_sel description mode mode if_sel vco_sel mod_type stby txstby shdn_bit if_pll_shdn rf_pll_shdn idle txgate h h x h h h h h shdn x x x l table 9. register and control pin states for key operating modes opctrl register control pins x = dont care config register downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 20 ______________________________________________________________________________________ max2361 0 90 if pll rf pll n.c. n.c. iflo shdn v reg 100pf tank h tank l v cc gc v cc v reg v reg v cc v cc v reg v bat v bat v bat v bat 19.68mhz tcxo 3300pf 10k ? 150 ? 0.033 f 33pf 33pf 0.033 f 3300pf 0.033 f 100pf 2.7pf 12pf 12pf 18pf 18pf 3 wire 10k ? 100pf 51k ? 1000pf 263mhz 228mhz txgate 10k ? 10k ? 10k ? 10k ? 33pf 33pf 3.3pf cell vco 18nh 7.5nh 15nh 1880mhz pcs rx 1960mhz 836mhz cell rx cell duplexer pcs duplexer diplexer 10k ? 15nh 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 45 -45 /2 /2 0 90 clk di cs dac dac dac idle lock pcs pa cell pa v reg 100pf 100pf bias pcs vco 33pf i q 150 ? v reg v reg 0.01 f 0.01 f 18nh 3.0pf figure 2. max2361 typical application circuit downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 21 max2363 0 90 if pll rf pll n.c. n.c. n.c. n.c. n.c. n.c. iflo n.c. n.c. n.c. n.c. shdn v reg 100pf tank v cc gc v cc v reg v reg v cc v cc v cc v bat v bat 19.68mhz tcxo 0.033 f 150 ? 3 wire 10k ? 47pf 51k ? 1000pf 263mhz txgate 33pf 33pf 18nh 15nh 1850mhz1880mhz pcs rx 1960mhz pcs duplexer 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 45 -45 /2 /2 0 90 clk bias di cs dac dac dac idle lock pcs pa v reg 100pf 100pf v reg 3300pf 10k ? 0.033 f 100pf 33pf 33pf pcs vco 2.7pf 12pf 12pf 10k ? 10k ? 15nh 0.033 f 3300pf 10k ? 100pf v bat i q v reg v reg 0.01 f 0.01 f 1880mhz1910mhz figure 3. max2363 typical application circuit downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 22 ______________________________________________________________________________________ max2365 0 90 if pll rf pll n.c. n.c. n.c. n.c. iflo n.c. v cc n.c. n.c. n.c. n.c. n.c. n.c. bias shdn v reg v reg 100pf tank l v cc gc v cc v reg v bat v reg v reg v bat 19.68mhz tcxo 3300pf 10k ? 0.033 f 150 ? 0.033 f 100pf 3.0pf 18pf 18pf 100pf 100pf 3 wire 10k ? 47pf 51k ? 1000pf 228mhz txgate 10k ? 10k ? 3.3pf 7.5nh cell rx 880mhz 836mhz cell duplexer 18nh 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 45 -45 /2 /2 0 90 clk di cs dac dac dac idle lock cell pa 33pf 33pf cell vco 0.033 f 3300pf 10k ? 100pf i q v reg v reg 0.01 f 0.01 f figure 4. max2365 typical application circuit downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 23 high-frequency bypass capacitors are required close to the pins with a dedicated via to ground. the 48- pin qfn-ep package provides minimal inductance ground by using an exposed paddle under the part. provide at least five low-inductance vias under the paddle to ground, to minimize ground inductance. use a solid ground plane wherever possible. any cutout in the ground plane may act as slot radiator and reduce it s shield effectiveness. keep the rf lo traces as short as possible to reduc e lo radiation and susceptibility to interference. i f t a nk de sign the low-band tank (tankl+, tankl-) and high-band tank (tankh+, tankh-) are fully differential. the e xter- nal tank components are shown in figure 6. the fre- quency of oscillation is determined by the followin g equation: c int = internal capacitance of tank port c d = capacitance of varactor c var = equivalent variable tuning capacitance c par = parasitic capacitance due to pc board pads and traces c cent = external capacitor for centering oscillation fre- quency c c = external coupling capacitor to the varactor table 10 shows possible component values for variou s oscillation frequencies. internal to the ic, the charge pump will have a lea kage of less than 10na. this is equivalent to a 300m ? shunt resistor. the charge-pump output must see an extremely high dc resistance of greater than 300m ? . this minimizes charge-pump spurs at the comparison frequency. make sure there is no solder flux under the varactor or loop filter. la yout i ssue s the max2361/max2363/max2365 ev kit can be used as a starting point for layout. for best performanc e, take into consideration power-supply issues as well as the rf, lo, and if layout. pow e r-supply la yout to minimize coupling between different sections of the ic, the ideal power-supply layout is a star configu ration, which has a large decoupling capacitor at a central v cc node. the v cc traces branch out from this node, each going to a separate v cc node in the max2361/ max2363/max2365 circuit. at the end of each trace i s a bypass capacitor with impedance to ground less th an 1 ? at the frequency of interest. this arrangement pro- f 2( c c c c)l c cc 2(c + c ) osc int cent var par var dc dc = +++ = 1 t cs t ch t cwl t cwh di clk cs t es b19 (msb) b18 b0 a3 a1 a0 (lsb) t cs > 50ns t ch > 10ns t cwh > 50ns t es > 50ns t cwl > 50ns t ew > 50ns t ew figure 5. 3-wire interface diagram l c d c cent c par c c c c c d max2361 max2363 max2365 c int -r n figure 6. tank port oscillator downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 24 ______________________________________________________________________________________ osc. freq. (mhz) l (nh) c cent (pf) c c (pf) c d 260.76 39 2.4 18 smv1763-079 400.0 30 3.3 18 smv1763-079 tankl 457.2 18 3.0 18 smv1763-079 330.0 22 4.3 12 smv1763-079 527.2 15 2.7 12 smv1763-079 tankh 760.0 11 1.2 9 smv1763-079 table 10. suggested component values for the if oscillators parameter condition value units ifl frequency if_sel = 0 228.6 mhz ifh frequency if_sel = 1 263.6 mhz rfl frequency range 824C849 mhz rfh0 frequency range 1850C1910 mhz lol frequency range 1052.6C1077.6 mhz loh frequency range 2113.6C2173.6 mhz lo input level lol or loh -7 dbm v gc = 2.4v, mpl = 0 +7 rfl output power v gc = 2.4v, mpl = 1 +10 dbm v gc = 2.4v, mpl = 0 +6 rfh0 output power v gc = 2.4v, mpl = 1 +10 dbm adjacent channel power ratio f offset = 30khz in 25khz bw -33 dbc alternate channel power ratio f offset = 60khz in 25khz bw -52 dbc mpl = 0, p rfh0 = +6dbm, f rfh0 = 1910mhz, measured at 1930mhz -134 mpl = 1, p rfh0 = +10dbm, f rfh0 = 1910mhz, measured at 1930mhz -131 mpl = 0, p rfl = +7dbm, f rfl = 849mhz, measured at 869mhz -134 receive band noise power mpl = 1, p rfl = +10dbm, f rfl = 849mhz, measured at 869mhz -131 dbm/hz table 11. cascaded tdma performance (from i/q input to pa driver output, iq_level = 0, v i_ = v q_ = 104mv rms , is136 nadc modulation or 415mv p-p differential with 0.1% 3db peak-average ratio.) downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 25 se le c t or guide vides local decoupling at each v cc pin. use at least one via per bypass capacitor for a low-inductance ground connection. also, connect the exposed paddle to pc board gnd with multiple vias to provide the l ow- est inductance possible. m a t c hing n e t w ork la yout the layout of a matching network can be very sensit ive to parasitic circuit elements. to minimize parasiti c inductance, keep all traces short and place compo- nents as close to the ic as possible. to minimize p ara- sitic capacitance, a cutout in the ground plane (an d any other planes) below the matching network compo- nents can be used. on the high-impedance ports (e.g., if inputs and ou t- puts), keep traces short to minimize shunt capacita nce. t a nk la yout keep the traces coming out of the tank short to red uce series inductance and shunt capacitance. keep the inductor pads and coupling capacitor pads small to minimize stray shunt capacitance. parameter conditions value units intermediate frequency if_sel = 1 380 mhz rfh0 frequency range 1920C1980 mhz loh frequency range 2300C2360 mhz lo input level loh -7 dbm maximum rfh0 output power v gc = 2.4v, mpl = 1 8 dbm minimum rfh0 output power zero_bias = 1, snr = 20db -75 dbm zero bias gain step from zero_bias = 1 to zero_bias = 0, v gc = 2.0v 27 db f offset = 3.5mhz in 30khz bw -60 f offset = 5mhz in 3.84mhz bw -45 adjacent channel power ratio f offset = 10mhz in 3.84mhz bw -58 dbc receive band noise power mpl= 1, p rfh0 = +8dbm, f rfh0 = 1950mhz, measured at 2140mhz -134 dbm/hz table 12. cascaded wcdma performance. (from i/q input to pa driver output, iq_level = 1, v i_ = v q_ = 146mv rms , uplink 3gpp modulation or 600mvp-p differential w ith 0.1% 3.25db peak-average ratio.) part max2361 1400 to 2360 800 to 1150 rf lo range (mhz) if range (mhz) 120 to 235 120 to 380 max2363 max2365 rf range (mhz) 800 to 1150 1400 to 2360 800 to 1000 120 to 380 120 to 235 1700 to 2000 1700 to 2000 800 to 1000 downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 26 ______________________________________________________________________________________ pin configura t ions ref n.c. n.c. tankh+ tankh- tankl+ tankl- iflo v cc shdn i- i+ rfl rfh0 lock v ccdrv idle v cc txgate ifinl+ ifinl- ifinh+ ifinh- bias 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 clk di cs ifouth- ifouth+ ifoutl- ifoutl+ gc v cc v cc q+ q- gnd rfh1 gnd gnd lol loh rfpll v ccrfcp rfcp v cc ifcp v ccifcp (t) qfn-ep max2361 ref n.c. n.c. tankh+ tankh- n.c. n.c. iflo v cc shdn i- i+ n.c. rfh0 lock v ccdrv idle v cc txgate n.c. n.c. ifinh+ ifinh- bias 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 clk di cs ifouth- ifouth+ n.c. n.c. gc v cc v cc q+ q- gnd rfh1 gnd gnd n.c. loh rfpll v ccrfcp rfcp v cc ifcp v ccifcp (t) qfn-ep max2363 ref n.c. n.c. n.c. n.c. tankl+ tankl- iflo v cc shdn i- i+ rfl n.c. lock v ccdrv idle v cc txgate ifinl+ ifinl- n.c. n.c. bias 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 clk di cs n.c. n.c. ifoutl- ifoutl+ gc v cc v cc q+ q- gnd n.c. gnd gnd lol n.c. rfpll v ccrfcp rfcp v cc ifcp v ccifcp (t) qfn-ep max2365 exposed-paddle gnd top view downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs ______________________________________________________________________________________ 27 pa c k a ge i nform a t ion (the package drawing(s) in this data sheet may not reflect the most current specifications. for the la test package outline info rmation go to www.maxim-ic.com/packages .) 32, 44, 48l qfn.eps h 1 2 21-0092 package outline32,44,48l qfn, 7x7x0.90 mm downloaded from: http:///
m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs 28 ______________________________________________________________________________________ pa c k a ge i nform a t ion (c ont inue d) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the la test package outline info rmation go to www.maxim-ic.com/packages .) u h 2 2 21-0092 package outline,32,44,48l qfn, 7x7x0.90 mm downloaded from: http:///
maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , s unnyva le , ca 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ____________________ 29 ? 2004 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. pa c k a ge i nform a t ion (c ont inue d) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the la test package outline info rmation go to www.maxim-ic.com/packages .) com ple t e dua l-ba nd qua dra t ure tra nsm it t e rs m ax 2 3 6 1 /m ax 2 3 6 3 /m ax 2 3 6 5 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm 1 d rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor detail b e l l1 proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d downloaded from: http:///

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